(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a static RAM the memory cells of which are each constituted by a pair of drive transistors and a pair of access transistors.
(2) Description of the Prior Art
An SRAM or static RAM usually has a pair of drive transistors constituting a flipflop in each of its memory cells which is in turn provided with an access transistor having the word line as the gate electrode. Each access transistor is connected to one of paired bit lines and data are read out from or written into the memory cells by way of data line or bit line pairs.
FIG. 1 is a circuit diagram of a conventional SRAM circuit, wherein memory cells 51 arranged in a matrix configuration are sandwitched between bit line pairs 52, 53 and selection of each memory cell 51 is made by one of a plurality of word lines 54 arranged substantially orthogonally to the bit line pairs 52, 53. A plurality of bit line pairs 52, 53 collected together constitute data line pairs 55, 56. Column gates 57 for selection of the bit line pairs are provided between the data line pairs 55, 56 and the bit line pairs 52, 53. A pull-up circuit 58 and an equalizer circuit 59 are provided between these data line pairs 55, 56. The pull-up circuit 58 pulls up the potential across the data lines 55, 56, while the equalizer circuit 59 short-circuits and equalizes the paired data lines. The pull-up circuit 58 and the equalizer circuit 59 are driven by pulse signals from an address transition detection circuit, which will be explained subsequently.
A write buffer circuit 60 is connected across the paired data lines for driving one of the paired data lines to a low level and the other of the data lines to a high level. Write gates 61, 61 are also provided between the write buffer circuit 60 and the data line pairs 55, 56 for controlling the connection therebetween. These write gates 61, 61 are controlled by a write gate drive circuit 62 in such a manner that the write buffer circuit 60 and the data line pairs 55, 56 are connected to each other only when both a write control signal CE.multidot.WE and a write recovery assist signal EQ supplied to the write gate control circuit 62 are at the high level.
FIG. 2 shows a load resistor type memory cell 51 having a pair of drive transistors 71, 72 having their sources grounded and having their drains cross-coupled to the sources of the counterpart drive transistors. Access transistors 75, 76 are connected to the drains between the bit lines 52, 53. These access transistors 75, 76 have their gates connected to word line 54. Bit line loads 65, 66 are provided at terminal ends of the bit lines 52, 53 between these terminal ends and source voltage Vcc. The write and read operations are performed with the selected word line 54 being at a high level with the access transistors 75, 76 being turned on, while data storage is performed with one of nodes 63, 64 being at a high level and with the other mode being at a low level.
With the above described circuit construction of the SRAM, the data lines 55, 56 are driven during the write operation to the fully swung state, that is to the state in which one of the data lines is at a low level which is about equal to the ground voltage and the other data line is at a high level which is about equal to the source voltage Vcc. For this reason, during shifting from the write cycle to the readout cycle, the data lines 55, 56 and the bit lines 52, 53 are pulled up to the high level by the operation of the pull-up circuit 58 and the equalizer circuit 59, usually before selection of the word lines 54, for preventing possible data destruction in the memory cell.
If the write buffer circuit 60 is in operation when the pull-up circuit 58 and the equalizer circuit 59 are in operation, it becomes difficult to pull up the data lines and the bit lines to the high level. Hence, when the pull-up circuit 58 and the equalizer circuit 59 are in operation, the write gates 61, 61 are simultaneously turned off for electrically isolating the write buffer circuit 60.
FIGS. 3a-3f show the waveforms of various signals during the conntinuous write mode in which a write cycle is followed by another write cycle. It is assumed that the WE (write enable) signal (b) is at a low level so that the CE.multidot.WE (write control) signal (d), which is an internal signal, is at a high level. If address signal (a) is changed in this state, a pulse having a pulse width t is produced as EQ or write recovery assist signal (c) from an address transition detection circuit which generates a pulse based on address transition. This pulse is supplied to a write gate drive circuit 62 to turn off write gates 61, 61. On the data line pair 55, 56, having the level (e), the pull-up circuit 58 and the equalizer circuit 59 come into operation at this time, so that one of the data lines brought to the low level is boosted and equalized. After boosting to some extent and resulting decrease in the potential difference, the potential (f) on the selected word line for the cycle is raised for selecting the memory cell 51 by the word line.
However, first of all, since the standby currents are maintained in the above described SRAM at a lower value, the resistances of the load resistors 73, 74 of FIG. 2 are set to higher values. Consequently, it is necessary to maintain a high write potential, that is a potential at one of modes 63, 64, for data storage, and the current practice is to reduce the leakage current at the junction points or the sub-threshold current of the drive transistor for procuring an operational margin of a drive transistor. As a method for reducing the sub-threshold current, it is known to elevate the threshold voltage Vth of the drive transistors 71, 72. However, these drive transistors 71, 72 are produced by the same process as that of producing the access transistors 75, 76, so that, when the threshold voltage Vth of the drive transistors 71, 72 is elevated, the threshold voltage Vth of the access transistors is simultaneously elevated; so that the write potential given by the source voltage Vcc less the threshold voltage Vth of the access transistors is also lowered. Consequently, it is difficult to produce a high operational margin of the memory cell.
Secondly, with the above described SRAM, the write or readout cycle is started by the transition of a plurality of addresses A.sub.0 to A.sub.x. In the case of a continuous write mode, should the address transition occur at a plurality of addresses, the pulse width of the write recovery assist signal EQ from the address transition detection circuit is also increased in dependence upon the temporary shift of the number of the addresses.
FIGS. 4a-4f shows waveforms of various signal for the continuous write mode. It is now assumed that the write enable or WE signal (b) is at a low level, that the write control or CE.multidot.WE signal (d) is at a high level, and that transition has occurred at the address signal (a) a plurality of addresses with a time difference .DELTA.t. The pulse width of the write recovery assist or EQ signal (c), generated at this time by the address transition detection circuit, which generates a pulse each time the address transition occurs, is increased to (t+.DELTA.t). Consequently, the write inhibit time during which the write gates 61, 61 are turned off, is lengthened, while the time interval during which the potential on the data line (e) is raised and equalized by the operation of the pull-up circuit 58 and the equalizer circuit 59 is also lengthened, thus giving rise to an inconvenience that the time interval of the write cycle is lengthened.
Such protraction of the write cycle is caused not only by the timing deviation in the transition at a plurality of the addresses, but by manufacture tolerances or fluctuations in the manufacture process of the semiconductor memory devices.